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preliminarysubject to change without notice order number: MPC7410PCPNS/d rev. 0, 10/2000 semiconductor products sector this document contains information on a new product under development by motorola. motorola reserves the right to change or discontinue this product without notice. ? motorola, inc., 2001. all rights reserved. motorola part numbers affected: xpc7410rx400pc xpc7410rx450pc xpc7410rx500pc xpc7410rx550pc xpc7410rx600pc mpc7410 part number speci?cation for the rx xxx pc series this document describes part number speci?c changes to recommended operating conditions and revised electrical speci?cations, as applicable, from those described in the general mpc7410 hardware speci?cations (order #: mpc7410ec/d). speci?cations provided in this part number speci?cation supersede those in the mpc7410 hardware speci?cations rev 0.3 (dated 3/2001) for these part numbers only; speci?cations not addressed herein are unchanged. this document is frequently updated. therefore, contact your motorola sales of?ce for the latest version. part numbers addressed in this document are listed in table 1. for more detailed ordering information see table 1.
2 mpc7410 part number speci?cation for the rxxxxpc series errata . errata this section summarizes design defects or errors (errata) that are known to exist for these parts. there may be additional errata that are not known or are not yet documented here which may cause the part to deviate from the functional description provided in the mpc7410 risc microprocessor users manual (order # mpc7410um/ad rev 0). the mpc7410 risc microprocessor users manual will be available in 4q00. contact your local motorola sales of?ce for later and/or more detailed description of the errata. table 1. part numbers addressed by this data sheet motorola part number operating conditions signi?cant differences from hardware speci?cation cpu frequency vdd t j (c) xpc7410rx400pc 400 mhz 2.0v50mv 0 to 65 modi?ed voltage & temperature speci?cation to achieve 400mhz frequency xpc7410rx450pc 450 mhz 2.0v50mv 0 to 65 modi?ed voltage & temperature speci?cation to achieve 450mhz frequency xpc7410rx500pc 500 mhz 2.0v50mv 0 to 65 modi?ed voltage & temperature speci?cation to achieve 500mhz frequency xpc7410rx550pc 550 mhz 2.0v50mv 0 to 65 modi?ed voltage & temperature speci?cation to achieve 550mhz frequency xpc7410rx600pc 600 mhz 2.0v50mv 0 to 65 modi?ed voltage & temperature speci?cation to achieve 600mhz frequency note: the x pre?x in a motorola powerpc part number designates a pilot production prototype as de?ned by motorola sop 3-13. these are from a limited production volume of prototypes manufactured, tested and q.a. inspected on a quali?ed technology to simulate normal production. these parts have only preliminary reliability and characterization data. before pilot production prototypes may be shipped, written authorization from the customer must be on ?le in the applicable sales of?ce acknowledging the quali?cation status and the fact that product changes may still occur while shipping pilot production prototypes. note: grayed-out 600mhz data are extrapolated values.
mpc7410 part number speci?cation for the rxxxxpc series 3 preliminarysubject to change without notice errata the known errata as of the date of this document are summarized below table 2. errata # problem description impact work-around 1 cache inhibited instruction fetches that hit in l2 direct mapped sram space may cause processor hang cache inhibited instruction fetches that hit in l2 direct mapped sram space when the instruction buffers are full may cause processor to not make forward progress systems using l2 direct mapped sram and mapping part of this space as cache inhibited 1. set l2rdis (bit 13) of msscr1, or 2. do not map instructions in the l2 direct mapped memory space as cache inhibited. 2 incorrect condition code on mismatched lwarx/stwcx pair a stwcx instruction may be performed without setting the condition code if the store hits in the l2 and the lwarx instruction that set the reservation is to another coherency granule. any code which uses mismatched lwarx/stwcx address pairs 1. avoid mismatched lwarx/stwcx address pairs, or 2. turn off the l2 3 tlbsync may hang in the presence of a dst the mpc7400 may not make forward progress if a dst has caused an mmu tablewalk, that mmu tablewalk was marked by a tlbie instruction, and a tlbsync instruction is pipelined the cycle after the mmu tablewal accesses the dl1 cache. any system which has an active dst engine while executing a tlbsync instruction in a privileged context insert a dssall instruction before a tlbsync instruction 4 queueing six transactions to secondary bus may hang the system queueing six transactions from a single max processor could use all data transaction queue resources and hang the system if forward progress cannot be made by allowing max to complete at least one outstanding transaction. any system which allows 6 outstanding transactions from a single processor and which has a secondary bus with characteristics as detailed in full description. 1. limit the number of outstanding transactions from a secondary bus to 5 in system logic, or 2. mark the memory space on the secondary bus as guarded and avoid dst(st)(t) and lmw instructions. 5 consecutive interrupts may be non-recoverable consecutive performance monitor, decrementer, or thermal management interrupts may become non-recoverable. any system which enables a combination of performance monitor, decrementer, or thermal management interrupts at the same time. avoid enabling any combination of performance monitor, decrementer, or thermal management interrupts at the same time. 6 disabling l2 cache may hang processor the mpc7410 may hang if the l2 cache is disabled during an outstanding instruction fetch. any system which executes code to disable the l2 cache. 1. mark the code that disables the l2 cache as cache inhibited, or 2. preload the code that disables the l2 cache into the instruction cache before execution.
4 mpc7410 part number speci?cation for the rxxxxpc series general general there are no changes to the features of the mpc7410 described in the mpc7410 hardware speci?cations (mpc7410ec/d). 1.1 dc electrical characteristics table 3 provides the recommended operating conditions for the mpc7410 part numbers described herein. table 7 provides the power consumption for the mpc7410 part at the frequencies described herein. table 3. recommended operating conditions characteristic symbol recommended value unit core supply voltage vdd 2.0v50mv v pll supply voltage avdd 2.0v50mv v l2 dll supply voltage l2avdd 2.0v50mv v processor bus supply voltage bvsel = hreset ovdd 2.5v125mv v bvsel = gnd ovdd 1.8v90mv v l2 bus supply voltage l2vsel = hreset l2ovdd 2.5v125mv v l2vsel = gnd l2ovdd 1.8v90mv v input voltage processor bus v in gnd to ovdd v l2 bus v in gnd to l2ovdd v jtag signals v in gnd to ovdd v die-junction temperature t j 0-65 c note: these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. table 4. power consumption for mpc7410 processor (cpu) frequency processor (cpu) frequency processor (cpu) frequency unit notes 400mhz 500mhz 600mhz full-on mode typical maximum 67 8 w 1, 3, 12 14 16 w 1, 2, 4 doze mode maximum 4 5 6 w 1, 2 nap mode maximum 2.0 2.25 2.5 w 1, 2 sleep mode maximum 2.0 2.25 2.5 w 1, 2
mpc7410 part number speci?cation for the rxxxxpc series 5 preliminarysubject to change without notice dc electrical characteristics 1.4.2.1 clock ac speci?cations table 8 provides the additional clock ac timing speci?cations described in this part number speci?cation. refer to the mpc7410 hardware speci?cation for the remaining frequencies . sleep modepll and dll disabled typical 0.5 0.5 0.5 w 1, 3 maximum 2.0 2.0 2.0 w 1, 2 notes: 1. these values apply for all valid processor bus and l2 bus ratios. the values do not include i/o supply power (ovdd and l2ovdd) or pll/dll supply power (avdd and l2avdd). ovdd and l2ovdd power is system dependent, but is typically <10% of vdd power. worst case power consumption for avdd = 15 mw and l2avdd = 15 mw. 2. maximum power is measured at vdd = 2.2v while running an entirely cache-resident, contrived sequence of instructions which keep the execution units, including altivec, maximally busy. 3. typical power is an average value measured at vdd = avdd = l2avdd = 2.15v, ovdd = l2ovdd = 2.5v in a system while running a codec application that is altivec intensive. 4. these values include the use of altivec. without altivec operation, estimate a 25% decrease. table 5. clock ac timing specifications at recommended operating conditions (see table 3.) characteristic symbol 400 mhz 450 mhz 500 mhz 550 mhz 600 mhz unit notes min max min max min max min max min max processor frequency f core 300 400 300 450 300 500 300 550 300 600 mhz vco frequency f vco 600 800 600 900 600 1000 600 1100 600 1200 mhz sysclk frequency f sysclk 33 100 33 100 33 100 33 100 33 100 mhz 1 sysclk cycle time t sysclk 7.5 30 7.5 30 7.5 30 7.5 30 7.5 30 ns sysclk rise and fall time t kr & t kf 1.0 1.0 1.0 1.0 1.0 ns 2 0.5 0.5 0.5 0.5 0.5 ns 3 sysclk duty cycle measured at ovdd/2 t khkl /t sys clk 40 60 40 60 40 60 40 60 40 60 % 4 sysclk jitter 150 150 150 150 150 ps 5 internal pll relock time 100 100 100 100 100 s6 notes:see general hardware speci?cation. table 4. power consumption for mpc7410 (continued) processor (cpu) frequency processor (cpu) frequency processor (cpu) frequency unit notes 400mhz 500mhz 600mhz
6 mpc7410 part number speci?cation for the rxxxxpc series dc electrical characteristics 1.4.2.2 processor bus ac speci?cations table 9 provides the processor bus ac timing speci?cations for the mpc7410 part described in this part number speci?cation . table 1. processor bus ac timing specifications 1 at vdd=avdd=2.0v50mv; 0 tj 65c, ovdd = 2.5v0.125v and ovdd = 1.8v0.090v, 60x bus at 100mhz parameter symbol 400, 450, 500, 550, 600 mhz unit notes min max mode select input setup to hreset t mvrh 8t sysclk 2,3,4,5 hreset to mode select input hold t mxrh 0 ns 2,3,5 setup times: address/transfer attribute transfer start (ts ) data/data parity ar tr y /shd0 /shd1 all other inputs t avkh t tsvkh t dvkh t arvkh t ivkh 1.4 1.4 1.4 1.4 1.4 ns10 6 7 8 input hold times: address/transfer attribute transfer start (ts ) data/data parity ar tr y /shd0 /shd1 all other inputs t axkh t tsxkh t dxkh t arxkh t ixkh 0 0 0 0 0 ns11 6 7 8 valid times: address/transfer attribute ts , abb , dbb data data parity artry/shd0/shd1 all other outputs t khav t khtsv t khdv t khdpv t kharv t khov 3.0 3.0 3.5 3.5 2.3 3.0 ns12 6 7 7 9 output hold times: address/transfer attribute ts , abb , dbb data/data parity ar tr y /shd0 /shd1 all other outputs t khax t khtsx t khdx t kharx t khox 0.75 0.75 0.6 0.75 0.75 ns13 6 7 9 sysclk to output enable t khoe 0.5 ns 14 sysclk to output high impedance (all except ts , abb/amon(0) , ar tr y /shd , dbb/dmon(0) t khoz 3.5 ns 15
mpc7410 part number speci?cation for the rxxxxpc series 7 preliminarysubject to change without notice dc electrical characteristics 1.4.2.3 l2 clock ac speci?cations table 1 provides the l2clk output ac timing speci?cations for the mpc7410 part described in this part number speci?cation sysclk to ts , abb/amon(0) , dbb/dmon(0) high impedance after precharge t khabpz 1.0 t sysclk 4,15, 16,17 maximum delay to ar tr y /shd0 /shd1 precharge t kharp 1t sysclk 4,17 sysclk to ar tr y /shd0 /shd1 high impedance after precharge t kharpz 2t sysclk 4,17 notes: see general hardware speci?cation. table 1. l2clk output ac timing specifications at recommended operating conditions (see table 3.) parameter symbol 400 mhz 450 mhz 500 mhz 550 mhz 600 mhz unit notes min max min max min max min max min max l2clk frequency f l2clk 150 200 150 225 150 250 150 275 150 300 mhz 1 l2clk cycle time t l2clk 5 6.67 4.4 6.67 4 6.67 3.6 6.67 3.3 6.67 ns l2clk duty cycle t chcl / t l2clk 50 50 50 50 50 % 2 internal dll-relock time 640 640 640 640 640 l2clk 4 dll capture window 200 200 200 200 200 ns 5 notes: see general hardware speci?cation. table 1. processor bus ac timing specifications 1 (continued) at vdd=avdd=2.0v50mv; 0 tj 65c, ovdd = 2.5v0.125v and ovdd = 1.8v0.090v, 60x bus at 100mhz parameter symbol 400, 450, 500, 550, 600 mhz unit notes min max
8 mpc7410 part number speci?cation for the rxxxxpc series dc electrical characteristics 1.4.2.4 l2 bus ac speci?cations table 1 provides the l2 bus interface ac timing speci?cations for the frequencies described in this part number speci?cation. table 1. l2 bus interface ac timing specifications at vdd=avdd=l2avdd= 2.05v50mv; 0 tj 65c, l2ovdd = 2.5v0.125v and l2ovdd =1.8v0.090v parameter symbol 400 mhz 450 mhz 500 mhz 550 mhz 600 mhz unit notes min max min max min max min max min max l2sync_in rise and fall time t l2cr & t l2cf 1.0 1.0 1.0 1.0 1.0 ns 1 setup times: data and parity t dvl2ch 1.5 1.375 1.250 1.125 1.0 ns2 input hold times: data and parity t dxl2ch 0.0 0.0 0.0 0.0 0.0 ns2 valid times: all outputs when l2cr[14-15] = 00 all outputs when l2cr[14-15] = 01 all outputs when l2cr[14-15] = 10 all outputs when l2cr[14-15] = 11 t l2chov - - - - 2.5 tbd tbd tbd - - - - 2.375 tbd tbd tbd - - - - 2.25 tbd tbd tbd - - - - 2.05 tbd tbd tbd - - - - 2.0 tbd tbd tbd ns 3,4 output hold times all outputs when l2cr[14-15] = 00 all outputs when l2cr[14-15] = 01 all outputs when l2cr[14-15] = 10 all outputs when l2cr[14-15] = 11 t l2chox 0.6 tbd tbd tbd - - - - 0.55 tbd tbd tbd - - - - 0.5 tbd tbd tbd - - - - 0.45 tbd tbd tbd - - - - 0.4 tbd tbd tbd - - - - ns3 l2sync_in to high impedance all outputs when l2cr[14-15] = 00 all outputs when l2cr[14-15] = 01 all outputs when l2cr[14-15] = 10 all outputs when l2cr[14-15] = 11 t l2choz - - - - 2.0 2.5 3.0 3.5 - - - - 2.0 2.5 3.0 3.5 - - - - 2.0 2.5 3.0 3.5 - - - - 2.0 2.5 3.0 3.5 - - - - 2.0 2.5 3.0 3.5 ns notes: see general hardware speci?cation
mpc7410 part number speci?cation for the rxxxxpc series 9 preliminarysubject to change without notice ordering information 1.10 ordering information table 1 provides the ordering information for the mpc7410 part described in this part number speci?cation. 1.10.1 part marking parts are marked as the example shown in figure 1.figure 1. figure 1. motorola part marking for bga device table 1. ordering information for the mpc7410 microprocessor package type device rev process mask code cpu frequency (mhz) motorola part number 360 cbga 1.2 hip 6 82k65d 400mhz xpc7410rx400pc 450mhz xpc7410rx450pc 500mhz xpc7410rx500pc 550mhz xpc7410rx550pc 600mhz xpc7410rx600pc bga notes: ccccc is the country of assembly (this space is left blank if parts are assembled in the united states) mmmmmm is the 6-digit mask number atwlyywwa is the traceability code xpc7410 rx450pc mmmmmm atwlyywwa 7410
10 mpc7410 part number speci?cation for the rxxxxpc series ordering information
mpc7410 part number speci?cation for the rxxxxpc series 11 preliminarysubject to change without notice ordering information
information in this document is provided solely to enable system and software implementers to use powerpc microprocessors. ther e are no express or implied copyright licenses granted hereunder to design or fabricate powerpc integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual perfor mance may vary over time. all operating parameters, including typicals must be validated for each customer application by customers technical ex perts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or autho rized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, o r for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer pu rchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employe es, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that moto rola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu. minato-ku, tokyo 106-8573 japan. 81-3-3440 -3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n .t., hong kong. 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors document comments: fax (512) 933-2625, attn: risc applications engineering world wide web addresses : http://www.motorola.com/powerpc http://www.motorola.com/netcomm http://www.motorola.com/coldfire MPC7410PCPNS/d digitaldna is a trademark of motorola, inc. the powerpc name, the powerpc logotype, and powerpc 603e are trademarks of international business machines corporation used by motorola under license from international business machines corporation.

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